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intel corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an intel product. no o ther circuit patent licenses are implied. information contained herein supersedes previously published specifications on these devices from intel . ? intel corporation, 1993 november 199 3 order number: 2722 0 6 -00 2 80960 s a embedded 32-bit microprocessor with 16-bit burst data bu s the 8096 0 s a is a member of intel?s i96 0 ? 32-bit processor family, which is designed especially for low cost embedded applications. it includes a 512-byte instruction cach e and a built-in interrupt controller. the 8096 0 s a has a large register set, multiple parallel execution units and a 16-bit burst bus. using advanced risc technology, this high performance processor is capable of execution rates in excess of 7. 5 million instructions per secon d * . the 8096 0 s a is well-suited for a wide range of cost sensitive embedded applications including non-impact printers, network adapters and i/o controllers . figure 1. the 80960 s a processor?s highly parallel architectur e * relative to digital equipment corporation?s vax-11/780 at 1 mips (vax-11? is a trademark of digital equipment corporation ) n high-performance embedded architectur e ? 2 0 mips* burst execution at 2 0 mh z ? 7. 5 mips sustained execution at 2 0 mh z n 512-byte on-chip instruction cach e ? direct mappe d ? parallel load/decode for uncached instruction s n multiple register set s ? sixteen global 32-bit register s ? sixteen local 32-bit register s ? four local register sets stored o n -chi p ? register scoreboardin g n pin compatible with 80960 s b n built-in interrupt controlle r ? 4 direct interrupt pin s ? 31 priority levels, 256 vector s n easy to use, high bandwidth 1 6 -bit bus ? 3 2 mbytes/s burs t ? up to 16 bytes transferred per burs t n 32-bit address space, 4 gigabyte s n 80-lead quad flat pack (eiaj qfp ) ? 84-lead plastic leaded chip carrier (plcc ) n software compatible with 80960ka/kb/ca/cf processor s instruction fetch unit 512-byte instruction cache instruction decoder micro- instruction sequencer micro- instruction rom 32-bit bus control logic 32-bit instruction execution unit 64- by 32-bit local register cache sixteen 32-bit global registers 32-bit address 16-bit burst bus
i i contents pag e 1.0 the i96 0 ? processo r ........................................................................................................................... 1 1.1 key performance features ................................................................................................................. 2 1.1.1 memory space and addressing modes ................................................................................... 4 1.1.2 data types ............................................................................................................................... 4 1.1.3 large register set ................................................................................................................... 4 1.1.4 multiple register sets .............................................................................................................. 5 1.1.5 instruction cache ..................................................................................................................... 6 1.1.6 register scoreboarding ........................................................................................................... 6 1.1.7 high bandwidth bus ................................................................................................................ 6 1.1.8 interrupt handling .................................................................................................................... 6 1.1.9 debug features ....................................................................................................................... 6 1.1.10 fault detection ....................................................................................................................... 7 1.1.11 built-in testability .................................................................................................................... 7 1.1.12 chmos ................................................................................................................................ .. 7 2.0 electrical specification s ............................................................................................................. 1 1 2.1 power and grounding ....................................................................................................................... 1 1 2.2 power decoupling recommendations .............................................................................................. 1 1 2.3 connection recommendations ......................................................................................................... 1 1 2.4 characteristic curves ....................................................................................................................... 1 1 2.5 test load circuit ............................................................................................................................... 1 3 2.6 absolute maximum ratings* .................................................................................................. 1 4 2.7 dc characteristics ............................................................................................................................ 1 4 2.8 ac specifications .............................................................................................................................. 1 5 3.0 mechanical data ................................................................................................................................ 2 1 3.1 packaging ................................................................................................................................ ......... 2 1 3.2 pin assignment ................................................................................................................................ . 2 1 3.3 pinout ................................................................................................................................ ................ 2 3 3.4 package thermal specifications ...................................................................................................... 2 7 3.5 stepping register information .......................................................................................................... 2 7 4.0 waveform s ................................................................................................................................ ........... 2 8 5.0 revision histor y ................................................................................................................................ 3 4 80960sa embedded 32-bit microprocessor with 16-bit burst data bu s
ii i list of figures pag e figure 1 the 80960sa processor?s highly parallel architecture ................................................................ 0 figure 2 80960sa programming environment ........................................................................................... 1 figure 3 instruction formats ...................................................................................................................... 4 figure 4 multiple register sets are stored on-chip .................................................................................. 5 figure 5 connection recommendation for lock .................................................................................... 1 1 figure 6 typical supply current vs. case temperature ........................................................................... 1 2 figure 7 typical current vs. frequency (room temp) ............................................................................. 1 2 figure 8 typical current vs. frequency (hot temp) ................................................................................. 1 3 figure 9 capacitive derating curve ......................................................................................................... 1 3 figure 10 test load circuit for three-state output pins ............................................................................ 1 3 figure 11 drive levels and timing relationships for 80960sa signals ..................................................... 1 5 figure 12 processor clock pulse (clk2) ................................................................................................... 1 9 figure 13 rese t signal timing ................................................................................................................. 1 9 figure 14 hold timing .............................................................................................................................. 2 0 figure 15 80-lead eiaj quad flat pack (qfp) package .......................................................................... 2 1 figure 16 84-lead plastic leaded chip carrier (plcc) package ............................................................. 2 2 figure 17 non-burst read and write transactions without wait states .................................................... 2 8 figure 18 quad word burst read transaction with 1, 0, 0, 0, 0, 0, 0, 0 wait states ................................ 2 9 figure 19 burst write transaction with 2, 1, 1, 1 wait states (6-8 bytes transferred) .............................. 3 0 figure 20 accesses generated by quad word read bus request, misaligned one byte from quad word boundary 1, 0, 0, 0, 0, 0, 0, 0 wait states ..................... 3 1 figure 21 interrupt acknowledge cycle ...................................................................................................... 3 2 figure 22 cold reset waveform ................................................................................................................ 3 3 list of tables table 1 80960sa instruction set .............................................................................................................. 3 table 2 memory addressing modes ......................................................................................................... 4 table 3 80960sa pin description: bus signals ........................................................................................ 8 table 4 80960sa pin description: support signals ................................................................................ 1 0 table 5 dc characteristics ..................................................................................................................... 1 4 table 6 80960sa ac characteristics (10 mhz) ...................................................................................... 1 6 table 7 80960sa ac characteristics (16 mhz) ...................................................................................... 1 7 table 8 80960sa ac characteristics (20 mhz) ...................................................................................... 1 8 table 9 80960sa qfp pinout ? in pin order ........................................................................................ 2 3 table 10 80960sa qfp pinout ? in signal order ................................................................................... 2 4 table 11 80960sa plcc pinout ? in pin order ...................................................................................... 2 5 table 12 80960sa plcc pinout ? in signal order ................................................................................. 2 6 table 13 80960sa qfp package thermal characteristics ...................................................................... 2 7 table 14 80960sa plcc package thermal characteristics .................................................................... 2 7 table 15 die stepping cross reference ................................................................................................... 2 7

1 80960s a 1.0 the i96 0 ? processo r the 8096 0 s a is a member of the 32-bit architecture from intel known as the i960 processor family. these microprocessors were especially designed to serve the needs of embedded applications. the embedded market includes applications as diverse as industrial automation, avionics, image processing, graphics and networking. these types of applications require high integration, low power consumption, quick interrupt response times and high performance. since time to market is critical, embedded micropr o - cessors need to be easy to use in both hardware and software designs . all members of the i960 processor family share a common core architecture which utilizes risc technology so that, except for special functions, the family members are object-code compatible. each new processor in the family adds its own special set of functions to the core to satisfy the needs of a specific application or range of applications in the embedded market. figure 2. 80960 s a programming environmen t architecturally defined data structures ffff fff f h instruction stream instruction execution processor state registers instruction pointer arithmetic controls process controls trace controls address space sixteen 32-bit global registers sixteen 32-bit local registers g0 g15 r0 r15 load store 0000 000 0 h instruction cache fetch four 80-bit control registers floating point registers
2 80960s a 1.1 key performance feature s the 8096 0 s a architecture is based on the most recent advances in microprocessor technology and is grounded in intel?s long experience in the design and manufacture of embedded microprocessors. many features contribute to the 8096 0 s a ?s exce p - tional performance : 1. large register set . having a large number of registers reduces the number of times that a processor needs to access memory. modern compilers can take advantage of this feature to optimize execution speed. for maximum flex i - bility, the 8096 0 s a provides thirty-two 32-bit register s . (see figure 2 . ) 2. fast instruction execution. simple functions make up the bulk of instructions in most programs so that execution speed can be improved by ensuring that these core instru c - tions are executed as quickly as possible. the most frequently executed instructions ? such as register-register moves, add/subtract, logical operations and shifts ? execute in one to two cycles. ( table 1 contains a list of instru c - tions. ) 3. load/store architecture . one way to improve execution speed is to reduce the number of times that the processor must access memory to perform an operation. as with other processors based on risc technology, the 8096 0 s a has a load/store architecture. as such, only the load and store instructions reference memory; all other instructions operate on registers. this type of architecture simplifies instruction decoding and is used in combination with other techniques to increase parallelism. 4. simple instruction formats . all instructions in the 8096 0 s a are 32 bits long and must be aligned on word boundaries. this alignment makes it possible to eliminate the instruction alignment stage in the pipeline. to simplify the instruction decoder, there are only five instruction formats; each instruction uses only one format. (see figure 3 . ) 5. overlapped instruction execution . load operations allow execution of subsequent instructions to continue before the data has been returned from memory, so that these instructions can overlap the load. the 8096 0 s a manages this process transparently to software through the use of a register scor e - board. conditional instructions also make use of a scoreboard so that subsequent unrelated instructions may be executed while the cond i - tional instruction is pending . 6. integer execution optimization . when the result of an arithmetic execution is used as an operand in a subsequent calculation, the value is sent immediately to its destination register. at the same time, the value is put on a bypass path to the alu, thereby saving the time that otherwise would be required to retrieve the value for the next operation . 7. bandwidth optimizations . the 8096 0 s a gets optimal use of its memory bus bandwidth because the bus is tuned for use with the on- chip instruction cache: instruction cache line size matches the maximum burst size for instruction fetches. the 8096 0 s a automatically fetches four words in a burst and stores them directly in the cache. due to the size of the cache and the fact that it is continually filled in anticipation of needed instructions in the program flow, the 8096 0 s a is relatively inse n - sitive to memory wait states. the benefit is that the 8096 0 s a delivers outstanding performance even with a low cost memory system . 8. cache bypass . if a cache miss occurs, the processor fetches the needed instruction then sends it on to the instruction decoder at the same time it updates the cache. thus, no extra time is spent to load and read the cache .
3 80960s a table 1. 80960 s a instruction se t data movemen t arithmeti c logica l bit and bit fiel d loa d stor e mov e load addres s ad d subtrac t multipl y divid e remainde r modul o shif t extended multipl y extended divid e an d not an d and no t o r exclusive o r not o r or no t no r exclusive no r no t nan d rotat e set bi t clear bi t not bi t check bi t alter bi t scan for bi t scan over bi t extrac t modif y compariso n branc h call/retur n faul t compar e conditional compar e compare and incremen t compare and decremen t unconditional branc h conditional branc h compare and branc h cal l call extende d call syste m retur n branch and lin k conditional faul t synchronize fault s debu g miscellaneou s decima l modify trace control s mar k force mar k atomic ad d atomic modif y flush local register s modify arithmetic control s scan byte for equa l test condition cod e move add with carr y subtract with carr y synchronou s synchronous loa d synchronous mov e
4 80960s a figure 3. instruction format s control compare and branch register to register memory access--- short memory access--- long opcode displacement opcode displacement reg/lit reg m displacement opcode opcode opcode reg reg reg reg/lit base base m modes mode ext?d op reg/lit x offset scale xx offset 1.1.1 memory space and addressing mode s the 8096 0 s a offers a linear programming environment so that all programs running on the processor are contained in a single address space. maximum address space size is 4 gigabytes ( 2 32 bytes) . for ease of use the 8096 0 s a has a small number of addressing modes, but includes all those necessary to ensure efficient execution of high-level languages such as c. table 2 lists the memory addressing modes . table 2. memory addressing mode s ? 12-bit offse t ? 32-bit offse t ? register-indirec t ? register + 12-bit offse t ? register + 32-bit offse t ? register + (index-register x scale-factor ) ? register x scale factor + 32-bit displacemen t ? register + (index-register x scale-factor) + 32- bit displacemen t scale-factor is 1, 2, 4, 8 or 1 6 1.1.2 data type s the 8096 0 s a recognizes the following data types : numeric : ? 8-, 16-, 32- and 64-bit ordinal s ? 8-, 16-, 32- and 64-bit integer s non-numeric : ? bi t ? bit fiel d ? triple word (96 bits ) ? quad-word (128 bits ) 1.1.3 large register se t the 8096 0 s a programming environment includes a large number of registers. in fact, 32 registers are available at any time. the availability of this many registers greatly reduces the number of memory accesses required to perform algorithms, which leads to greater instruction processing speed . there are two types of general-purpose register: local and global. the global registers consist of sixteen 32-bit registers (g0 though g15 ) . these registers perform the same function as the general-
5 80960s a purpose registers provided in other popular micr o - processors. the term global refers to the fact that these registers retain their contents across procedure calls . the local registers, on the other hand, are procedure specific. for each procedure call, the 8096 0 s a allocates 16 local registers (r0 through r15). each local register is 32 bits wide . 1.1.4 multiple register set s to further increase the efficiency of the register set, multiple sets of local registers are stored on-chip (see figure 4 ). this cache holds up to four local register frames, which means that up to three procedure calls can be made without having to access the procedure stack resident in memory. although programs may have procedure calls nested many calls deep, a program typically oscillates back and forth between only two to three levels. as a result, with four stack frames in the cache, the prob a - bility of having a free frame available on the cache when a call is made is very high. in fact, runs of representative c-language programs show that 80% of the calls are handled without needing to access memory . if four or more procedures are active and a new procedure is called, the 8096 0 s a moves the oldest local register set in the stack-frame cache to a procedure stack in memory to make room for a new set of registers. global register g15 is the frame pointer (fp) to the procedure stack . global registers are not exchanged on a procedure call, but retain their contents, making them available to all procedures for fast parameter passing . figure 4. multiple register sets are stored on-chi p r 15 r 0 31 0 one of four local register sets register cache local register set
6 80960s a 1.1.5 instruction cach e to further reduce memory accesses, the 8096 0 s a includes a 512-byte on-chip instruction cache. the instruction cache is based on the concept of locality of reference; most programs are not usually executed in a steady stream but consist of many branches, loops and procedure calls that lead to jumping back and forth in the same small section of code. thus, by maintaining a block of instructions in cache, the number of memory references required to read instructions into the processor is greatly reduced . to load the instruction cache, instructions are fetched in 16-byte blocks; up to four instructions can be fetched at one time. an efficient prefetch algorithm increases the probability that an instruction will already be in the cache when it is needed . code for small loops often fits entirely within the cache, leading to a great increase in processing speed since further memory references might not be necessary until the program exits the loop. similarly, when calling short procedures, the code for the calling procedure is likely to remain in the cache so it will be there on the procedure?s return . 1.1.6 register scoreboardin g the instruction decoder is optimized in several ways. one optimization method is the ability to overlap instructions by using register scoreboarding . register scoreboarding occurs when a load moves a variable from memory into a register. when the instruction initiates, a scoreboard bit on the target register is set. once the register is loaded, the bit is reset. in between, any reference to the register contents is accompanied by a test of the scoreboard bit to ensure that the load has completed before processing continues. since the processor does not need to wait for the load to complete, it can execute additional instructions placed between the load and the instruction that uses the register contents, as shown in the following example : ld data_2, r 4 ld data_2, r 5 unrelated instructio n unrelated instructio n add r4, r5, r 6 in essence, the two unrelated instructions between load and add are executed ?for free? (i.e., take no apparent time to execute) because they are executed while the register is being loaded. up to three load instructions can be pending at one time with three corresponding scoreboard bits set. by exploiting this feature, system programmers and compiler writers have a useful tool for optimizing execution speed . 1.1.7 high bandwidth bu s the 8096 0 s a cpu resides on a high-bandwidth address/data bus. the bus provides a direct comm u - nication path between the processor and the memory and i/o subsystem interfaces. the processor uses the bus to fetch instructions, manipulate memory and respond to interrupts. bus features include : ? 16-bit data path multiplexed onto the lower bits of the 32-bit address pat h ? eight 16-bit half-word burst capability which allows transfers from 1 to 16 bytes at a tim e ? high bandwidth reads and writes with 32 mbytes/s burst (at 20 mhz ) table 3 defines bus signal names and functions; table 4 defines other component-support signals such as interrupt lines . 1.1.8 interrupt handlin g the 8096 0 s a can be interrupted in one of two ways: by the activation of one of four interrupt pins or by sending a message on the processor?s data bus. the 8096 0 s a is unusual in that it automatically handles interrupts on a priority basis and can keep track of pending interrupts through its on-chip interrupt controller. two of the interrupt pins can be configured to provide 8259a-style handshaking for expansion beyond four interrupt lines . 1.1.9 debug feature s the 8096 0 s a has built-in debug capabilities. there are two types of breakpoints and six trace modes. debug features are controlled by two internal 32-bit registers, the process-controls word and the trace- controls word. by setting bits in these control words, a software debug monitor can closely control how the processor responds during program execution .
7 80960s a the 8096 0 s a provides two hardware breakpoint registers on-chip which, by using a special command, can be set to any value. when the instruction pointer matches either breakpoint register value, the breakpoint handling routine is automat i - cally called . the 8096 0 s a also provides software breakpoints through the use of two instructions: mark and fmark. these can be placed at any point in a program and cause the processor to halt execution at that point and call the breakpoint handling routine. the breakpoint mechanism is easy to use and provides a powerful debugging tool . tracing is available for instructions (single step execution), calls and returns and branching. each trace type may be enabled separately by a special debug instruction. in each case, the 8096 0 s a executes the instruction first and then calls a trace handling routine (usually part of a software debug monitor). further program execution is halted until the routine completes, at which time execution resumes at the next instruction. the 8096 0 s a ?s tracing mechanisms, implemented completely in hardware, greatly simplify the task of software test and debug . 1.1.10 fault detectio n the 8096 0 s a has an automatic mechanism to handle faults. fault typ e s include trace and arithmetic faults. when the processor detects a fault, it automatically calls the appropriate fault handling routine and saves the current instruction pointer and necessary state information to make efficient recovery possible. like interrupt handling routines, fault handling routines are usually written to meet the needs of specific applications and are often included as part of the operating system or kernel . for each of the fault types, there are numerous subtypes that provide specific information about a fault . the fault handler can use this specific info r - mation to respond correctly to the fault . 1.1.11 built-in testabilit y upon reset, the 8096 0 s a automatically conducts an exhaustive internal test of its major blocks of logic. then, before executing its first instruction, it does a zero check sum on the first eight words in memory to ensure that the memory image was programmed correctly. if a problem is discovered at any point during the self-test, the 8096 0 s a asserts its fai l pin and will not begin program execution. self test takes approximately 24,00 0 cycles to complete . system manufacturers can use the 8096 0 s a ?s self- test feature during incoming parts inspection. no special diagnostic programs need to be written. the test is both thorough and fast. the self-test capability helps ensure that defective parts are discovered before systems are shipped and, once in the field, the self-test makes it easier to distinguish between problems caused by processor failure and problems resulting from other causes . 1.1.12 chmo s the 8096 0 s a is fabricated using intel?s chmos iv (complementary high speed metal oxide semico n - ductor) process. the 8096 0 s a is available at 1 0 and 1 6 mhz in the qfp package and at 1 0 , 1 6 and 20 mhz in the plcc package .
8 80960s a table 3. 8096 0 s a pin description: bus signals (sheet 1 of 2 ) nam e typ e descriptio n clk 2 i system cloc k provides the fundamental timing for 8096 0 s a systems. it is divided by two inside the 8096 0 s a to generate the internal processor clock . a31:1 6 o t.s . address bu s carries the upper 16 bits of the 32-bit physical address to memory. it is valid throughout the burst cycle; no latch is required . ad15:1, d 0 i/o t.s . address/data bu s carries the low order 32-bit addresses and 16-bit data to and from memory. ad15:4 must be latched since the cycle following the address cycle carries data on the bus . a3: 1 o t.s . address bu s carries the word addresses of the 32-bit address to memory. these three bits are incremented during a burst access indicating the next word address of the burst access. note that a3:1 are duplicated with ad3:1 during the address cycle . al e o t.s . address latch enabl e indicates the transfer of a physical address. al e is asserted during a t a cycle and deasserted before the beginning of the t d state. it is active high and floats to a high impedance state during a hold cycle ( t h ) . a s o t.s . address statu s indicates an address state. a s is asserted every t a state and deasserted during the following t d state. a s is driven high during reset . w / r o t.s . write/rea d specifies, during a t a cycle, whether the operation is a write or read. it is latched on-chip and remains valid during t d cycles . de n o t.s . data enabl e is asserted during t d cycles and indicates transfer of data on the ad lines. the ad lines should not be driven by an external source unless de n is asserted. when de n is asserted, outputs from the previous cycle are guaranteed to be three-stated. in addition, de n deasserted indicates inputs have been captured; therefore input hold times can be disregarded. de n is driven high during reset . dt / r o t.s . data transmit / receiv e indicates the direction of data transfer to and from the bus. it is low during t a and t d cycles for a read or interrupt acknowledgment; it is high during t a and t d cycles for a write. dt / r never changes state when de n is asserted. dt / r is driven high during reset . read y i read y indicates that data on ad lines can be sampled or removed. if read y is not asserted during a t d cycle, the t d cycle is extended to the next cycle by inserting a wait state ( t w ) . i/o = input/output, o = output, i = input, o.d. = open drain, t.s. = three-stat e
9 80960s a loc k i/o o.d . bus loc k prevents bus masters from gaining control of the bus during read/modify/write (rmw) cycles. the processor or any bus agent may assert loc k . at the start of a rmw operation, the processor examines the loc k pin. if the pin is already asserted, the processor waits until it is not asserted. if the pin is not asserted, the processor asserts loc k during the t a cycle of the read transaction. the processor deasserts loc k in the t a cycle of the write transaction. while loc k is asserted, a bus agent can perform a normal read or write but not a rmw operation. the processor also asserts loc k during interrupt-acknowledge transa c - tions . do not leave loc k unconnected. it must be pulled high for the processor to function properly . once mod e : the loc k pin is sampled during reset. if it is asserted low at the end of reset, all outputs will be three-stated until the part is reset again. once mode is used in conjunction with an in-circuit emulator . be1: 0 o t.s . byte enable line s specify which data bytes (up to two) on the bus take part in the current bus cycle. be 1 corresponds to ad15:8; be 0 corresponds to ad7:1, d0 . the byte enable lines are asserted appropriately during each data cycle . initialization failur e indicates that the processor has failed to initialize correctly. the failure state is indicated by a combination of blas t asserted and be1: 0 not asserted. this condition occurs after rese t is deasserted and before the first bus transaction begins. fai l is asserted while the processor performs a self-test. if the self-test completes successfully, fai l is deasserted. the processor then performs a zero checksum on the first eight words of memory, if it fails, fai l is asserted for a second time and remains asserted; if it passes, system initialization continues and fai l remains deasserted . hol d i hol d indicates a request from an external bus master to acquire the bus. when the processor receives hold and grants bus control to another master, it floats its three-state bus lines, then asserts hlda and enters the t h state. when hold is deasserted, the processor deasserts hlda and enters the t i or t a state . hld a o t.s . hold acknowledg e notifies an external bus master that the processor has relinquished control of the bus. this signal is always driven. at reset it is driven low . blas t / fai l o t.s . burst las t indicates the last data cycl e ( t d ) of a burst access. it is asserted low during the last t d and associated wit h t w cycles in a burst access . initialization failur e indicates that the processor has failed to initialize correctly. the failure state is indicated by a combination of blas t asserted and be1: 0 not asserted. this condition occurs after rese t is deasserted and before the first bus transaction begins. fai l is asserted while the processor performs a self-test. if the self-test completes successfully, fai l is deasserted. the processor then performs a zero checksum on the first eight words of memory, if it fails, fai l is asserted for a second time and remains asserted; if it passes, system initialization continues and fai l remains deasserted . table 3. 8096 0 s a pin description: bus signals (sheet 2 of 2 ) nam e typ e descriptio n i/o = input/output, o = output, i = input, o.d. = open drain, t.s. = three-stat e
1 0 80960s a table 4. 80960 s a pin description: support signals nam e typ e descriptio n rese t i rese t clears the processor?s internal logic and causes it to reinitialize . during rese t assertion, the input pins are ignored (except for int 0 , int1, int 3 , loc k ), the three-state output pins are placed in a high impedance state (except for dt / r , de n , and a s ) and other output pins are placed in their non-asserted states . rese t must be asserted for at least 41 clk2 cycles for a predictable reset. optionally, for a synchronous reset, the low and high transition of rese t should occur after the rising edge of both clk2 and the external bus clk and before the next rising edge of clk2 . the interrupt pins indicate the initialization sequence executed. typical initia l - ization requires driving only int 0 and int 3 to a high state. the reset conditions follow : int 0 int1 int 3 loc k action take n 1 x 1 1 run self test (core initialization ) 0 0 1 1 disable self-tes t 0 1 x x reserve d x x 0 x reserve d x x x 0 once mode (see loc k pin ) int 0 i interrupt 0 indicates a pending interrupt. to signal an interrupt in a synchronous system, this pin ? as well as the other interrupt pins ? must be enabled by being deasserted for at least one bus cycle and then asserted for at least one additional bus cycle. in an asynchronous system, the pin must remain deasserted for at least two system clock cycles and then asserted for at least two more system clock cycles. the interrupt control register must be programmed with an interrupt vector before using this pin . int 0 is sampled during reset to determine if the self-test sequence is to be executed . int 1 i interrupt 1 , like int 0 , provides direct interrupt signaling. int1 is sampled during reset to determine if the self-test sequence is to be executed . int2/int r i interrupt2/interrupt reques t : the interrupt control register determines how this pin is interpreted. if int2, it has the same interpretation as the int 0 and int1 pins. if intr, it is used to receive an interrupt request from an external interrupt controller . int 3 / int a i/ o t.s . interrupt3/interrupt acknowledg e : the interrupt control register determines how this pin is interpreted. if int 3 , it has the same interpretation as the int 0 and int1 pins. if int a , it is used as an output to control interrupt acknowledge transactions. the int a output is latched on-chip and remains valid during t d cycles; as an output, it is open-drain. int 3 must be pulled high during reset . n c n/ a not connecte d indicates pins should not be connected. never connect any pin marked nc; these pins may be reserved for factory use . i/o = input/output, o = output, i = input, o.d. = open drain, t.s. = three-stat e
1 1 80960s a 2.0 electrical specification s 2.1 power and groundin g the 8096 0 s a is implemented in chmos iv technology and therefore has modest power requir e - ments. its high clock frequency and numerous output buffers (address/data, control, error and arbitration signals) can cause power surges as multiple output buffers simultaneously drive new signal levels. for clean on-chip power distribution, v c c and v s s pins separately feed the device?s functional units. power and ground connections must be made to all 8096 0 s a power and ground pins. on the circuit board, all v c c pins must be strapped closely together, preferably on a power plane; all v s s pins should be strapped together, preferably on a ground plane. 2.2 power decoupling recommendation s place a liberal amount of decoupling capacitance near the 8096 0 s a . when driving the bus the processor can cause transient power surges, parti c - ularly when connected to a large capacitive load . low inductance capacitors and interconnects are recommended for best high frequency electrical performance. inductance is reduced by shortening board traces between the processor and decoupling capacitors as much as possible. 2.3 connection recommendation s for reliable operation, always connect unused inputs to an appropriate signal level. in particular, if one or more interrupt lines are not used, they should be pulled up. no inputs should ever be left floating . the loc k open-drain pin requires a pullup resistor whether or not the pin is used as an output. figure 5 shows the recommended resistor value . do not connect external logic to pins marked nc . figure 5. connection recommendation for loc k 2.4 c haracteristic curve s figure 6 shows typical supply current requirements over the operating temperature range of the processor at supply voltage ( v c c ) of 5v. figure 7 shows the typical power supply current ( i c c ) that the 8096 0 s a requires at various operating frequencies when measured at three input voltage ( v c c ) levels . for a given output current ( i o l ) the curve in figure 8 shows the worst case output low voltage ( v o l ). figure 9 shows the typical capacitive derating curve for the 8096 0 s a measured from 1.5v on the system clock (clk) to 0.8v on the falling edge and 2.0v on the rising edge of the bus address/data (ad) signals. 91 0 w v cc open-drain output
1 2 80960s a figure 6. typical supply current vs. case temperatur e figure 7. typical current vs. frequency (room temp ) v c c = 5.0v p o w e r s u p p l y c u r r e n t ( m a ) case temperature (c) 20 mhz 16 mhz 10 mhz 100 150 200 250 300 350 -10 0 10 20 30 40 50 60 70 80 90 100 110 0 5 10 15 20 25 operating frequency (mhz) 4.5v 5.0v 5.5v t y p i c a l s u p p l y c u r r e n t ( m a ) temp = +22c 250 225 200 175 150 125 100
1 3 80960s a figure 8. typical current vs. frequency (hot temp ) 0 5 10 15 20 25 operating frequency (mhz) t y p i c a l s u p p l y c u r r e n t ( m a ) temp = +85c 4.5v 5.0v 5.5v 300 250 200 150 100 50 0 figure 9. capacitive derating curv e 0 20 40 60 80 100 30 25 20 15 10 t h r e e - s t a t e o u t p u t capacitive load (pf) (temp = +85c, v cc = 4.5v) 5 0 rising falling x x x v a l i d d e l a y ( n s ) 2.5 test load circui t figure 1 0 illustrates the load circuit used to test the 8096 0 s a ?s output pins . figure 10. test load circuit for three-state output pin s three-state output c l = 50 pf for all signals c l
1 4 80960s a 2.6 absolute maximum ratings * paramete r maximum ratin g o perating temperature (plcc) ........... 0c to +85c cas e operating temperature (qfp) ............ 0c to +100c cas e storage temperature .............................. ?65c to +150 c voltage on any pin (plcc) ................. ?0.5v to vcc +0.5 v voltage on any pin (qfp) ............... ?0.25v to vcc +0.25 v power dissipation ....................................... 1.9w ( 2 0 mhz ) notic e : this is a production data sheet. the specifications are subject to change without notice . *warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability . 2.7 dc characteristic s 8096 0 s a (1 0 and 1 6 mhz qfp) t cas e = 0c to +100 c, v c c = 5v 5% 8096 0 s a (10 and 16 mhz plcc) t cas e = 0c to +85 c, v c c = 5v 10 % 8096 0 s a (20 mhz plcc) t cas e = 0c to +85 c, v c c = 5v 5 % table 5. d c characteristics symbo l paramete r mi n ma x unit s note s v i l input low voltag e ?0. 3 +0. 8 v v i h input high voltag e 2. 0 v c c + 0. 3 v v c l clk2 input low voltag e ?0. 3 +0. 8 v v c h clk2 input high voltag e 0.7 v c c v c c + 0. 3 v v o l output low voltag e 0.4 5 0.4 5 v v i o l = 4.0 m a i o l = 6 ma, loc k pi n v o h output high voltag e 2. 4 v all ts, -2.5 m a (1 ) i c c power supply current: 10 mhz-qfp 10 mhz-plcc 16 mhz-plc c 20 mhz-plc c 24 0 24 0 30 0 34 0 ma ma m a m a t cas e = 0 0 c t cas e = 0 0 c t cas e = 0 0 c t cas e = 0 0 c i li 1 input leakage current, except int 0 , loc k 1 5 a 0 v i n v c c i li 2 input leakage current, int 0 , loc k ?30 0 a v i n = 0.45 v (2 ) i o l output leakage curren t 1 5 a c i n input capacitanc e 1 0 p f f c = 1 mh z (3 ) c o output capacitanc e 1 2 p f f c = 1 mhz (3 ) c cl k clock capacitanc e 1 0 p f f c = 1 mhz (3 ) notes : 1. not measured for open-drain output . 2. int 0 and loc k have internal pullup devices . 3. input, output and clock capacitance are not tested .
1 5 80960s a 2.8 ac specification s this section describes the ac specifications for the 8096 0 s a pins. all input and output timings are specified relative to the 1.5v level of the rising edge of clk2 and refer to the time at which the signal crosses 1.5v (for output delay and input setup). all ac testing should be done with input voltages of 0.4v and 2.4v, except for the clock (clk2) which should be tested with input voltages of 0.45v and 0.7 x v c c . see figure 1 1 and tables 6, 7 and 8 for timing relationships for the 8096 0 s a signals . figure 11. drive levels and timing relationships for 80960 s a signal s a b c d a b c 1.5v 1.5v 1.5v 1.5v t 6 1.5v 1.5v t 7 1.5v 1.5v valid output t 6 t 8 t 8 t 13 t 14 1.5v 1.5v valid output t 9 2.0v 2.0v 2.0v 2.0v 0.8v 0.8v 0.8v 0.8v edge clk2 outputs: ad15:1, a3:1, d0, w / r , de n , blas t , hlda, loc k , inta ale dt / r inputs: ad15:1, d0, int2, int3 hold lock ready t 9 t 10 t 11 t 12 t 11 a 31:16, be1:0, int 0 , int1, as t 6as t 6as valid input
1 6 80960s a table 6. 8096 0 s a ac characteristics (10 mhz) symbo l paramete r mi n ma x unit s note s input cloc k t 1 processor clock period (clk2 ) 5 0 12 5 n s v i n = 1.5 v t 2 processor clock low time (clk2 ) 8 n s v t = 10% poin t = v c l + ( v c h ? v c l ) x 0. 1 t 3 processor clock high time (clk2 ) 8 n s v t = 90% poin t = v c l + ( v c h ? v c l ) x 0. 9 t 4 processor clock fall time (clk2 ) 1 0 n s v t = 90% to 10% point (1 ) t 5 processor clock rise time (clk2 ) 1 0 n s v t = 10% to 90% point (1 ) synchronous output s t 6 output valid dela y 2 3 1 n s t 6a s a s output valid dela y 2 2 5 n s t 7 ale widt h t 1 - 1 1 n s t 8 ale output valid dela y 4 3 3 n s t 9 output float dela y 2 2 0 n s (2 ) synchronous input s t 1 0 input setup 1 1 0 n s t 1 1 input hol d 2 n s t 1 2 input setup 2 1 3 n s t 1 3 setup to ale inactiv e 1 0 n s t 1 4 hold after ale inactiv e 8 n s t 1 5 rese t hol d 3 n s (3 ) t 1 6 rese t setu p 5 n s (3 ) t 1 7 rese t widt h 205 0 n s 41 clk2 periods minimu m notes : 1. processor clock (clk2) rise time and fall time are not tested . 2. a float condition occurs when the maximum output current becomes less than i l o . float delay is not tested, but should be no longer than the valid delay . 3. meeting rese t setup and hold times is an optional method of synchronizing your clocks. if you decide to use an asy n - chronous reset, synchronizing the clock can be accomplished by using a s .
1 7 80960s a table 7. 8096 0 s a ac characteristics (16 mhz) symbo l paramete r mi n ma x unit s note s input cloc k t 1 processor clock period (clk2 ) 31.2 5 12 5 n s v i n = 1.5 v t 2 processor clock low time (clk2 ) 8 n s v t = 10% poin t = v c l + ( v c h ? v c l ) x 0. 1 t 3 processor clock high time (clk2 ) 8 n s v t = 90% poin t = v c l + ( v c h ? v c l ) x 0. 9 t 4 processor clock fall time (clk2 ) 1 0 n s v t = 90% to 10% point (1 ) t 5 processor clock rise time (clk2 ) 1 0 n s v t = 10% to 90% point (1 ) synchronous output s t 6 output valid dela y 2 2 5 n s t 6a s a s output valid dela y 2 2 1 n s t 7 ale widt h t 1 - 1 1 n s t 8 ale output valid dela y 2 2 2 n s t 9 output float dela y 2 2 0 n s (2 ) synchronous input s t 1 0 input setup 1 1 0 n s t 1 1 input hol d 2 n s t 1 2 input setup 2 1 3 n s t 1 3 setup to ale inactiv e 1 0 n s t 1 4 hold after ale inactiv e 8 n s t 1 5 rese t hol d 3 n s (3 ) t 1 6 rese t setu p 5 n s (3 ) t 1 7 rese t widt h 128 1 n s 41 clk2 periods minimu m notes : 1. processor clock (clk2) rise time and fall time are not tested . 2. a float condition occurs when the maximum output current becomes less than i l o . float delay is not tested, but should be no longer than the valid delay . 3. meeting rese t setup and hold times is an optional method of synchronizing your clocks. if you decide to use an asy n - chronous reset, synchronizing the clock can be accomplished by using a s .
1 8 80960s a table 8. 8096 0 s a ac characteristics (20 mhz) symbo l paramete r mi n ma x unit s note s input cloc k t 1 processor clock period (clk2 ) 2 5 12 5 n s v i n = 1.5 v t 2 processor clock low time (clk2 ) 6 n s v t = 10% poin t = v c l + ( v c h ? v c l ) x 0. 1 t 3 processor clock high time (clk2 ) 6 n s v t = 90% poin t = v c l + ( v c h ? v c l ) x 0. 9 t 4 processor clock fall time (clk2 ) 1 0 n s v t = 90% to 10% point (1 ) t 5 processor clock rise time (clk2 ) 1 0 n s v t = 10% to 90% point (1 ) synchronous output s t 6 output valid dela y 2 2 0 n s t 6a s a s output valid dela y 2 2 0 n s t 7 ale widt h t 1 - 1 1 n s t 8 ale output valid dela y 2 1 8 n s t 9 output float dela y 2 1 7 n s (2 ) synchronous input s t 1 0 input setup 1 7 n s t 1 1 input hol d 2 n s t 1 2 input setup 2 1 3 n s t 1 3 setup to ale inactiv e 1 0 n s t 1 4 hold after ale inactiv e 8 n s t 1 5 rese t hol d 3 n s (3 ) t 1 6 rese t setu p 5 n s (3 ) t 1 7 rese t widt h 102 5 n s 41 clk2 periods minimu m notes : 1. processor clock (clk2) rise time and fall time are not tested . 2. a float condition occurs when the maximum output current becomes less than i l o . float delay is not tested, but should be no longer than the valid delay . 3. meeting rese t setup and hold times is an optional method of synchronizing your clocks. if you decide to use an asy n - chronous reset, synchronizing the clock can be accomplished by using a s .
1 9 80960s a figure 12. processor clock pulse (clk2 ) figure 13. rese t signal timing high level (min) 0 . 7 v cc low level (max) 0.8v t 1 t 3 t 5 t 4 t 2 90% 10% 1.5 v clk2 clk reset outputs a b c d a b c t 15 t 16 int 0 , int1, int 3 , lock initialization parameters t 17 not e : initialization parameters must be set up at least four clk2 periods before the first clk2 ?a? edge.
2 0 80960s a figure 14. hold timin g t h t h t h clk2 clk hold hlda t 12 t 11 t 6 t 6
2 1 80960s a 3.0 mechanical dat a 3.1 pack a g i n g the 8096 0 s a is available in two package types: ? 80-lead quad flat pack (eiaj qfp). shown in figure 1 5 . ? 84-lead plastic leaded chip carrier (plcc). shown in figure 1 6 . dimensions for both package types are given in the intel packagin g handbook (order #240800). 3.2 pin assignmen t the qfp and plcc have different pin assignments. the qfp pins are numbered in order from 1 to 80 around the package perimeter. the plcc pins are numbered in order from 1 to 84 around the package perimeter. tables 9 and 1 0 list the function of each qfp pin; tables 1 1 and 1 2 list the function of each plcc pin . v c c and gnd connections must be made to multiple v c c and gnd pins. each v c c and gnd pin must be connected to the appropriate voltage or ground and externally strapped close to the package. it is reco m - mended that you include separate power and ground planes in your circuit board for power distribution . pins identified as nc (no connect) should never be connecte d . figure 15. 80-lead eiaj quad flat pack (qfp) packag e a s ad1 ad2 v ss ad3 ad4 ad5 ad6 a d 7 a d 8 a d 9 a d 1 0 a d 1 1 a d 1 2 a d 1 3 a d 1 4 a d 1 5 a 1 6 a 1 7 a 1 8 a 1 9 a 2 0 a 2 1 a 2 2 v ss a23 a24 a25 b l a s t h o l d v s s r e s e t v c c c l k 2 i n t 3 / i n t a i n t 2 / i n t r i n t 1 i n t 0 v c c v c c n c v s s v s s v c c v c c v s s v s s v cc v cc nc v ss v ss v ss v cc v c c v cc h l d a ale a1 a2 a3 d0 w / r ready d t / r b e 0 be1 v s s l o c k d e n v s s v s s v c c v c c 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 80 79 78 77 76 75 74 73 72 71 70 69 68 67 22 23 24 25 26 27 28 29 30 31 32 33 a26 a27 a28 a29 a30 a31 s80960sa-20 xxxxxxxx xxxxxx xxxxxx
2 2 80960s a . figure 16. 84-lead plastic leaded chip carrier (plcc) packag e a s a d 1 a d 2 v ss a d 3 a d 4 a d 5 a d 6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 a16 a17 a18 a19 a20 a 2 1 a 2 2 v ss a 2 3 a 2 4 a 2 5 blast hold v s s reset v c c clk2 int 3 / inta int2/intr int1 int0 v c c v c c n c v s s v s s v cc v c c v ss v ss v cc v cc nc v ss v ss nc v ss v cc v cc v cc hlda a l e a 1 a 2 a 3 d 0 w / r r e a d y dt / r b e 0 b e 1 v s s lock den n c n c v s s v s s n c v c c v c c 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 22 23 24 25 26 27 28 29 30 31 32 33 a 2 6 a 2 7 a 2 8 a 2 9 a 3 0 a 3 1 n80960sa-20 xxxxxxxx xxxxxx xxxxxx
2 3 80960s a 3.3 pinou t table 9. 80960 s a qfp pinout ? in pin orde r pi n signa l pi n signa l pi n signa l pi n signa l 1 a2 2 2 1 v c c 4 1 be 0 6 1 v c c 2 a2 1 2 2 v s s 4 2 v c c 6 2 v s s 3 a2 0 2 3 v c c 4 3 v s s 6 3 n c 4 a1 9 2 4 v s s 4 4 clk 2 6 4 a s 5 a1 8 2 5 ad 6 4 5 rese t 6 5 v s s 6 a1 7 2 6 ad 5 4 6 int 0 6 6 al e 7 a1 6 2 7 ad 4 4 7 int 1 6 7 read y 8 v c c 2 8 ad 3 4 8 int2/int r 6 8 a3 1 9 v s s 2 9 ad 2 4 9 int 3 / int a 6 9 a3 0 1 0 ad1 5 3 0 ad 1 5 0 hld a 7 0 a2 9 1 1 ad1 4 3 1 d 0 5 1 v c c 7 1 a2 8 1 2 v c c 3 2 v s s 5 2 v s s 7 2 v s s 1 3 v s s 3 3 v c c 5 3 hol d 7 3 v c c 1 4 ad1 3 3 4 a 3 5 4 w / r 7 4 a2 7 1 5 ad1 2 3 5 a 2 5 5 de n 7 5 a2 6 1 6 ad1 1 3 6 v c c 5 6 dt / r 7 6 a2 5 1 7 ad1 0 3 7 v s s 5 7 blas t 7 7 v c c 1 8 ad 9 3 8 a 1 5 8 loc k 7 8 v s s 1 9 ad 8 3 9 n c 5 9 v c c 7 9 a2 4 2 0 ad 7 4 0 be 1 6 0 v s s 8 0 a2 3 notes : do not connect any external logic to any pins marked nc .
2 4 80960s a table 10. 80960 s a qfp pinout ? in signal orde r signa l pi n signa l pi n signa l pi n signa l pi n a 1 3 8 a1 8 5 d 0 3 1 v c c 5 1 a 2 3 5 a1 9 4 de n 5 5 v c c 5 9 a 3 3 4 a2 0 3 dt / r 5 6 v c c 6 1 ad 1 3 0 a2 1 2 hld a 5 0 v c c 7 3 ad 2 2 9 a2 2 1 hol d 5 3 v c c 7 7 ad 3 2 8 a2 3 8 0 int 0 4 6 v c c 8 ad 4 2 7 a2 4 7 9 int 1 4 7 v s s 1 3 ad 5 2 6 a2 5 7 6 int2/int r 4 8 v s s 2 2 ad 6 2 5 a2 6 7 5 int 3 / int a 4 9 v s s 2 4 ad 7 2 0 a2 7 7 4 loc k 5 8 v s s 3 2 ad 8 1 9 a2 8 7 1 n c 3 9 v s s 3 7 ad 9 1 8 a2 9 7 0 n c 6 3 v s s 4 3 ad1 0 1 7 a3 0 6 9 read y 6 7 v s s 5 2 ad1 1 1 6 a3 1 6 8 rese t 4 5 v s s 6 0 ad1 2 1 5 al e 6 6 v c c 1 2 v s s 6 2 ad1 3 1 4 a s 6 4 v c c 2 1 v s s 7 2 ad1 4 1 1 be 0 4 1 v c c 2 3 v s s 7 8 ad1 5 1 0 be 1 4 0 v c c 3 3 v s s 9 a1 6 7 blas t 5 7 v c c 3 6 v s s 6 5 a1 7 6 clk 2 4 4 v c c 4 2 w / r 5 4 notes : do not connect any external logic to any pins marked n.c .
2 5 80960s a table 11. 80960 s a plcc pinout ? in pin orde r pi n signa l pi n signa l pi n signa l pi n signa l 1 v c c 2 2 v s s 4 3 v s s 6 4 hol d 2 n c 2 3 n c 4 4 v c c 6 5 n c 3 a2 7 2 4 ad1 3 4 5 a 3 6 6 w / r 4 a2 6 2 5 ad1 2 4 6 a 2 6 7 de n 5 a2 5 2 6 ad1 1 4 7 v c c 6 8 dt / r 6 v c c 2 7 ad1 0 4 8 v s s 6 9 blas t 7 v s s 2 8 ad 9 4 9 a 1 7 0 loc k 8 a2 4 2 9 ad 8 5 0 n c 7 1 v c c 9 a2 3 3 0 ad 7 5 1 be 1 7 2 v s s 1 0 a2 2 3 1 v c c 5 2 be 0 7 3 v c c 1 1 a2 1 3 2 v s s 5 3 v c c 7 4 v s s 1 2 a2 0 3 3 v c c 5 4 v s s 7 5 n c 1 3 a1 9 3 4 v s s 5 5 clk 2 7 6 a s 1 4 a1 8 3 5 ad 6 5 6 rese t 7 7 v s s 1 5 a1 7 3 6 ad 5 5 7 int 0 7 8 al e 1 6 a1 6 3 7 ad 4 5 8 int 1 7 9 read y 1 7 v c c 3 8 ad 3 5 9 int2/int r 8 0 a3 1 1 8 v s s 3 9 d 2 6 0 int 3 / int a 8 1 a3 0 1 9 ad1 5 4 0 d 1 6 1 hld a 8 2 a2 9 2 0 ad1 4 4 1 d 0 6 2 v c c 8 3 a2 8 2 1 v c c 4 2 n c 6 3 v s s 8 4 v s s notes : do not connect any external logic to any pins marked nc .
2 6 80960s a table 12. 80960 s a plcc pinout ? in signal orde r signa l pi n signa l pi n signa l pi n signa l pi n a 1 4 9 a1 8 1 4 dt / r 6 8 v c c 4 4 a 2 4 6 a1 9 1 3 hld a 6 1 v c c 4 7 a 3 4 5 a2 0 1 2 hol d 6 4 v c c 5 3 d 0 4 1 a2 1 1 1 int 0 5 7 v c c 6 ad 1 4 0 a2 2 1 0 int 1 5 8 v c c 6 2 ad 2 3 9 a2 3 9 int2/int r 5 9 v c c 7 1 ad 3 3 8 a2 4 8 int 3 / int a 6 0 v c c 7 3 ad 4 3 7 a2 5 5 loc k 7 0 v s s 1 8 ad 5 3 6 a2 6 4 n c 2 v s s 2 2 ad 6 3 5 a2 7 3 n c 2 3 v s s 3 2 ad 7 3 0 a2 8 8 3 n c 4 2 v s s 3 4 ad 8 2 9 a2 9 8 2 n c 5 0 v s s 4 3 ad 9 2 8 a3 0 8 1 n c 6 5 v s s 4 8 ad1 0 2 7 a3 1 8 0 n c 7 5 v s s 5 4 ad1 1 2 6 al e 7 8 read y 7 9 v s s 6 3 ad1 2 2 5 a s 7 6 rese t 5 6 v s s 7 ad1 3 2 4 be 0 5 2 v c c 1 v s s 7 2 ad1 4 2 0 be 1 5 1 v c c 1 7 v s s 7 4 ad1 5 1 9 blas t 6 9 v c c 2 1 v s s 7 7 ad1 6 1 6 clk 2 5 5 v c c 3 1 v s s 8 4 a1 7 1 5 de n 6 7 v c c 3 3 w / r 6 6 notes : do not connect any external logic to any pins marked nc .
2 7 80960s a 3.4 package thermal specification s the 80960 s a is specified for operation when case temperature is within the range 0c to +85c (plcc) or 0c to 100c (qfp). measure case temperature at the top center of the package. ambient tempe r - ature can be calculated from : t j = t c + p * q jc t a = t j - p * q ja t c = t a + p * [ q j a - q j c ] compute p by multiplying the maximum voltage by the typical current at maximum temperature. values for q j a and q j c for various airflows are given in table 1 3 for the qfp package and in table 1 4 for the plcc package. i c c at maximum temperature is typically 80 percent of specified i c c maximum (cold) . table 13. 80960 s a qfp package thermal characteristic s thermal resistance ? c/wat t paramete r airflow ? ft./min (m/sec ) 0 5 0 10 0 20 0 40 0 60 0 80 0 q junction-to-ambient (case measured in the middle of the top of the package) (no heatsink ) 5 9 5 7 5 4 5 0 4 4 4 0 3 8 q junction-to-cas e 1 1 1 1 1 1 1 1 1 1 1 1 1 1 notes : this table applies to 80960 s a qfp soldered directly to board . table 14. 80960 s a plcc package thermal characteristic s thermal resistance ? c/wat t paramete r airflow ? ft./min (m/sec ) 0 5 0 10 0 20 0 40 0 60 0 80 0 100 0 q junction-to-ambient (no heatsink ) 3 4 3 2 29. 5 2 8 2 5 2 3 2 1 20. 5 q junction-to-cas e 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 notes : this table applies to 80960 s a plcc soldered directly to board . 3.5 stepping register informatio n upon reset, register g0 contains die stepping info r - mation. table 1 5 shows the relationship between the number in g0 and the current die steppin g the current numbering pattern in g0 may not be consistent with past or future steppings of this product . table 15. die stepping cross referenc e register g0 die steppin g 01010101 h c- 1
2 8 80960s a 4.0 waveform s figures 1 7 , 1 8 , 1 9 , 2 0 and 2 1 show waveforms for various transactions on the 80960 s a ?s bus. figure 2 2 shows a cold reset functional waveform . figure 17. non-burst read and write transactions without wait state s t a t d t r t a t d t r clk2 clk ale as a31:16 w / r dt / r den ready blast be1:0 valid valid invalid a3:1 addr addr data d a15:4, d15:0 valid valid
2 9 80960s a figure 18. quad word burst read transaction with 1, 0, 0, 0, 0, 0, 0, 0 wait state s t a t w t d t d t d t d t d t d t d t d t r clk2 clk ale as be1:0 w / r dt / r den ready blast d d d d d d d d a3:1 a15:4, d15:0 a31:16 valid 000 001 010 011 100 101 110 111 addr
3 0 80960s a figure 19. burst write transaction with 2, 1, 1, 1 wait states (6-8 bytes transferred ) t a t w t w t d t w t d t w t d t w t d t r clk2 clk ale as be1:0 w / r dt / r den ready blast a3:1 a15:4, d15:0 a31:16 valid addr data data data data valid valid valid valid 00 00 x0 0x
3 1 80960s a figure 20. accesses generated by quad word read bus request, misaligned one byte from quad word boundary 1, 0, 0, 0, 0, 0, 0, 0 wait state s t a t w t d t d t d t d t d t d t d t d t r c l k 2 c l k a l e a s b e 1 w / r d t / r d e n b l a s t a 3 : 1 a 1 5 : 4 , d 1 5 : 0 a 3 1 : 1 6 v a l i d a d d r t a t w t d t r b e 0 a d d r d d d d d d d d d v a l i d 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 r e a d y
3 2 80960s a figure 21. interrupt acknowledge cycl e clk2 t a t d t r t i t i t i t i t i t a t w t d t r a15:4, ale as inta dt / r den lock clk w / r blast a31:16 d15:0 addr add data a3:1 1 1 0 be1:0 ready 1 0 1 0
3 3 80960s a figure 22. cold reset wavefor m r e s e t c l k 2 c l k v c c a s , d t / r , d e n , l o c k ( o ) h l d a b l a s t / f a i l a l e , a 3 1 : 1 6 , a 1 5 : 4 , a 3 : 1 , d 1 5 : 0 , b e 1 : 0 , w / r i n t 0 , i n t 1 , i n t 3 , l o c k ( i ) v c c a n d c l k 2 s t a b l e t o r e s e t h i g h , m i n i m u m 4 1 c l k 2 p e r i o d s i n i t i a l i z a t i o n p a r a m e t e r s s e t u p t o f i r s t a e d g e , m i n i m u m 4 c l k 2 p e r i o d s f i r s t b u s a c t i v i t y i n t e r n a l s e l f - t e s t , a p p r o x i m a t e l y 9 4 , 0 0 0 c l k 2 p e r i o d s ( i f s e l e c t e d ) a b c d t a a b c d a b c d a b c d a b c d a b c d 4 8 , 0 0 0 v a l i d
3 4 80960s a 5.0 revision histor y this data sheet supersedes data sheet 2722 0 6 -00 1 and applies only to those devices identified as the current stepping in section 3.5 . the sections significantly changed since the previous revisio n are : data sheet 270917-004 applied to both the 80960sa and the 80960sb. the 80960 s a was then documented alone in data sheet 2722 0 6 -001. the sections significantly changed between revisions -004 of the sa/sb data sheet and 2722 0 6 -001 of the s a data sheet were : sectio n last rev . descriptio n 2.3 connection recommendations (pg. 11 ) -00 1 removed two loc k pin connection recommendation figures and added figure 5 to reflect the new loc k pin connection recommendatio n of a single 91 0 w pullup resistor . 2.5 test load circuit (pg. 13 ) -00 1 obsolete figure (test load circuit for open-drain output pins) removed to reflect current test conditions . 2.7 dc characteristics (pg. 14 ) -00 1 i o l value at 0.45v improved. was: 2.5 ma is: 4.0 m a loc k pin i o l value at 0.45v relaxed . was: 12 ma is: 6 m a loc k pin i o l value at 0.60v deleted . 80960sa 16 mhz qfp added to product list . 3.5 stepping register information (pg. 27 ) -00 1 new section added . sectio n last rev . descriptio n 2.3 connection recommendations (pg. 11 ) -00 4 deleted corresponding graph of open drain voltage vs. ou t - put current . figure 6. typical supply current vs. case temperature (pg. 11 ) figure 7. typical current vs. fr e - quency (room temp) (pg. 12 ) figure 8. typical current vs. fr e - quency (hot temp) (pg. 12 ) -00 4 regraphed ne w data in three graphs instead of two . table 5. dc characteristics (pg. 15 ) -00 4 input leakage current ( i li 2 ) specification added to acc u - rately describe leakage of in t 0 and loc k as inputs . i c c max reduced : power supply current: was: is: 10 mhz 280 24 0 16 mhz 350 30 0 notes : page numbers refer to 80960 s a data sheet number 2722 0 6 -001 .
3 5 80960s a table 6. 80960sa ac characteristics (10 mhz) (pg. 17 ) table 7. 80960sa ac characteristics (16 mhz) (pg. 18) . -00 4 t 7 minimum specification improved : power supply current: was: is : 10 mhz 24 ns t 1 - 11 n s 16 mhz 15 ns t 1 - 11 n s table 8. 80960sa ac characteristics (20 mhz) (pg. 19 ) -00 4 new 20 mhz specification table added for 80960sa c-step . table 11. 80960sa plcc pinout ? in pin order (pg. 26 ) -00 4 q j a increased to reflect smaller die size and lower i c c . table 11. 80960sa plcc pinout ? in pin order (pg. 26 ) -00 4 q j a and q jc increased to reflect smaller die size and lower i c c . the sections significantly changed between revisions -003 and -004 of the 80960sa/sb data sheet were : sectio n last rev . descriptio n dc characteristic s -00 3 operating temperature for plcc package changed : was: t cas e = 0c to +100 c is: t cas e = 0c to +85 c the test program has not changed . table 9. 80960sa and 80960sb qfp pinout ? in pin orde r -00 3 signal a12 incorrectly shown as pin 28; is now co r - rectly shown as pin 38. note added to clarify no co n - nect pins . sectio n last rev . descriptio n notes : page numbers refer to 80960 s a data sheet number 2722 0 6 -001 .

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